![藤本 邦昭](https://researchmap.jp/fujimoto_kuniaki/avatar.png)
Fujimoto Kuniaki
- 教授
- 学位:博士(工学)
基本情報
所属
- Undergraduate School of Humanities and Science / Department of Human Information Engineering
- Undergraduate School of Industrial and Welfare Engineering / Department of Electrical Engineering and Computer Science
- Graduate School of Science and Technology / Course of Science and Technology
詳細情報
研究分野
- Manufacturing technology (mechanical, electrical/electronic, chemical engineering) Electronic devices and equipment
- Informatics Computer systems
受賞
- Best Paper Award A Wide Range Manhattan Distance Search Circuit Using Neuron CMOS Inverters
- Contribution Award
- Excellent Paper Award A Minimum Manhattan Distance Retrieving Circuit Using Neuron CMOS Inverters
- Outstanding Paper Award A Study on Flash Type A/D Converter Using Neuron CMOS Inverter
論文
DESIGN OF FREQUENCY MULTIPLIER BASED ON DOUBLE-EDGE COUNTER AND ITS ANALYSIS
A STUDY OF A MINIMUM EUCLIDEAN DISTANCE SEARCH CIRCUIT FOR AN ASSOCIATIVE MEMORY
DIGITAL FREQUENCY-LOCKED LOOP WITH WIDE LOCK-IN RANGE AND LOW FREQUENCY ERROR BASED ON MULTI-PHASE CLOCK
APPROACHES TO REMOTE LEARNING DURING COVID-19 IN THE SCHOOL OF INDUSTRIAL AND WELFARE ENGINEERING, TOKAI UNIVERSITY
An Electronic Neuron Using Interconnect Capacitance and Applied to a Variable Logic Circuit
DIGITAL FREQUENCY-LOCKED LOOP WITH LOW FREQUENCY ERROR BASED ON MULTI-PHASE CLOCK
A Study of Digitally Controlled Oscillator Based on Multi-Phase Clock
Digital frequency-locked loop based on double-edge counter
Detection of Land Cover Changes before and after the 2016 Kumamoto Earthquake in Japan Using Remote Sensing for Evaluation of Environmental Impacts
Multiple output of similarity data by recalling type associative memory using neuron CMOS inverter
Analysis by fpd for neuron CMOS variable logic circuit with fg calibration
A flash type a/d converter using neuron cmos inverters with threshold compensation circuits
A reset type 2-mode digital fll with anti-pseudo-lock function and phase control
Voltage characteristics of a hamming distance search circuit in voltage domain using clocked neuron cmos inverter
A 1+n/k frequency divider unrelated to duty ratio of multi-phase clock
A digitally controlled oscillator using 1+1/k frequency divider based on multi-phase clock
Multiple-frequency digital phase-locked loop based on multiphase clock divider with constant pulse interval
Short-circuit-current reduction by using a clocked neuron cmos inverter in a time-domain data coincidence detector
A WIDE RANGE MANHATTAN DISTANCE SEARCH CIRCUIT USING NEURON CMOS INVERTERS
Multiple frequency digital phase-locked loop based on multi-phase clock divider with constant pulse interval
講演?口頭発表等
- Land Cover Change Detection before and after the 2016 Kumamoto Earthquake Using Remote Sensing
- A-1-22 A Study on Dividing Circuit with Multi-Phase Input Clocks
- A Study on Dividing Ratio Changeable m Multiplication Circuit with Delay Circuit.
- A-1-12 A Study on Analog Digital Mixed PLL
- Dividing Ratio Changeable All Digital Phase Locked Loop with Low Jitter
- A Proposition on Reset Type Fast Pull-in PLL Using Frequency difference
- A Proposition on Multiple Frequency Digital PLL Using Fractional Divider
- A Proposition on Digital FLL using pulse counter
- A proposal for a non-pseudo-locked FLL
- A Proposition on Digital PLL using pulse counter
- A Proposal on Pulse Train Arithmetic Circuits Using Switched-Current
- A Proposal on Pulse Train Multiplier Circutis Using Switched-Capacitor.
- A study of digital locked loop on pulse number count system
- A Proposal on Pulse number Arithmetic Circuits Using Switched-Capacitor
- A proposition on Noisie-less DC-AC Converter using Switched Capacitor Circuits
- CMOS Ternary Cycling Circuits ang Ternary D-Iatch Circuits
共同研究?競争的資金等の研究課題
A Study on a Low Power Variable Logic Circuit Using Neuron CMOS Inverters
Associative Memory Using Neuron CMOS Inverters
High-Speed and Low Power Consumption AD Converter Using Neuron MOSFET
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